1. Technical Field
Various embodiments relate to a semiconductor apparatus, and more particularly, to a memory apparatus which includes nonvolatile memory cells.
2. Related Art
A conventional DRAM includes a memory cell constituted by a capacitor, and data is stored by charging or discharging charges to and from the memory cell. However, since the capacitor has leakage current due to the characteristics thereof, the DRAM has a disadvantage in that it is a volatile memory. In order to overcome the disadvantage, memories which are nonvolatile and do not need the retention of data have been developed. In particular, attempts have continuously been made to realize nonvolatility by modifying the structure of a memory cell. One of these attempts is a resistive memory apparatus which includes a resistive memory cell. The resistive memory apparatus may store multi-level data according to a resistance distribution of the resistive memory cell.
FIG. 1 is a diagram schematically showing the configuration of a conventional nonvolatile memory apparatus 10. In FIG. 1, the conventional nonvolatile memory apparatus 10 includes a memory cell 11 and first to fourth transistors N1, N2, N3 and N4. The memory cell 11 is formed of a resistive substance of which resistance value changes according to a temperature or current, and has different resistance values according to the data stored therein. Also, the memory cell 11 includes a diode to allow current to flow in one direction.
The first transistor N1 supplies sensing current to sense the data stored in the memory cell 11. The first transistor N1 receives a bias voltage VB and applies a power supply voltage VPPSA to a sensing node SAI. The second transistor N2 is turned on in response to a clamping signal VCLAMP and serves to control the voltage applied to the memory cell 11 not to exceed a threshold. The third transistor N3 is turned on in response to a bit line select signal BLS when a bit line to which data access is to be implemented is selected. The fourth transistor N4 is turned on in response to a word line select signal WLS when a word line to which data access is to be implemented is selected.
FIG. 2 is a diagram schematically showing the configuration of another conventional nonvolatile memory apparatus 20. The conventional nonvolatile memory apparatus 20 includes a sense amplifier 22 in addition to the configuration of the nonvolatile memory apparatus 10 of FIG. 1, to sense multi-level data stored in a memory cell. Thus, the same reference characters of FIG. 1 will be used throughout FIG. 2 to refer to the same or like parts. The sense amplifier 22 is connected with a sensing node SAI and receives a sensing voltage VSEN from the sensing node SAI. The sense amplifier 22 compares the sensing voltage VSEN with first to third reference voltages REF1, REF2 and REF3, and generates a data output signal DOUT.
The conventional nonvolatile memory apparatuses 10 and 20 sense the data stored in memory cells 11 and 21 by changing the voltage of the sensing node SAI. The first transistor N1 is turned on when the bias voltage VB is applied, and is configured to supply a constant amount of current to the sensing node SAI. The current flows through the memory cells 11 and 21. Accordingly, the voltage level of the sensing node SAI changes according to the resistance values of the memory cells 11 and 21. That is to say, when the resistance values of the memory cells 11 and 21 are large, the voltage of the sensing node SAI has a high level, and when the resistance values of the memory cells 11 and 21 are small, the voltage of the sensing node SAI has a low level. In this way, in the conventional nonvolatile memory apparatuses 10 and 20, the constant amount of current is supplied to the sensing node SAI, and the data stored in the memory cells 11 and 21 are sensed through a change in the voltage level of the sensing node SAI according to the resistance values of the memory cells 11 and 21.
Further, in order to reliably sense a change in the voltage level of the sensing node SAI according to the resistance values of the memory cells 11 and 21, a boosting voltage VPPSA is used as the power supply voltage. In general, the boosting voltage VPPSA may be generated, as a voltage with a level higher than the level of a power supply voltage applied from an outside, through a pumping circuit.
Moreover, the sense amplifier 22 necessarily needs a plurality of reference voltages to sense data stored in the memory cell 21. Namely, when the memory cell 21 stores 2-bit data, total three reference voltages are needed to differentiate 00, 01, 10 and 11.